Node Controller: NumaChip-3 High-Level Specifications

Overview:

• • Innovative Shared memory, Scalable and Cache Coherent System Interconnect Architecture

  • Supports high-performance 2^nd Generation Intel® Xeon® Scalable Processors (Purley and Whitley Platforms) processor nodes

  • Supports Intel Ultra Path Interconnect 1.0 (UPI 1.0) technology

  • ASIC implementation capable of supporting (2S, 4S, 8S, 16S, 32S) system configurations

Scalability:

• • Supports upto 11.2 GT/s full-width data-rate per UPI port

  • Performance improvement through full-directory snoop filter architecture

  • Implements 2-UPI ports capable of connecting 2 components with UPI interface

  • Supports 16 connected UNC chips capable of handling 32 Home Agent NIDs

  • Supports two parallel data-planes by doubling the number of UNCs per system

Security:

• • Superior RAS capabilities for the highest level of service

  • ECC protection on all important data structures (payload buffers, snoop filter, snoop filter cache, microcode instruction storage)

  • Support for viral and poison state mechanisms for handling error propagation and graceful shutdown

NumaChip

The Numascale technology includes a modular chip microarchitecture that allows system vendors to choose the right configuration to support their performance requirements. The microarchitecture includes several parallel micro-coded memory transaction engines with a large number of outstanding memory transactions, a memory controller for the cache and memory tags, a cross-bar switch for the interconnect fabric and a number of interconnect fabric link controllers. This means that there is no need for any external interconnect fabric switch, all switching is performed on-chip and the interconnect fabric is implemented with wiring through a PCB backplane or cables. The entire design for NumaConnect™ is implemented in a single FPGA or ASIC called NumaChip™ depending on the system vendor’s requirements.